Part 17: Advanced Topics

Introduction to Advanced Embedded Topics

Throughout this series, you’ve mastered the fundamentals — power systems, passive components, MCU circuits, PCB layout, testing, and production. Now we push beyond the comfortable realm of SPI buses and GPIO pins into the high-speed, security-critical, silicon-level domain where today’s most demanding embedded systems live. This chapter covers the technologies that separate a competent hardware engineer from an advanced one.

High-Speed Interfaces

Impedance-Controlled PCB Design

# Microstrip impedance calculator — outer layer trace
# Uses simplified Hammerstad-Jensen equation

import math

# PCB parameters
Er = 4.4        # Dielectric constant (FR4)
h = 0.2         # Dielectric height (mm) — distance to reference plane
w = 0.15        # Trace width (mm)
t = 0.035       # Copper thickness (mm) — 1 oz copper

# Effective dielectric constant
w_h = w / h
Er_eff = (Er + 1) / 2 + (Er - 1) / 2 * (1 / math.sqrt(1 + 12 / w_h))

# Characteristic impedance (microstrip)
if w_h <= 1:
    Z0 = (60 / math.sqrt(Er_eff)) * math.log(8 / w_h + w_h / 4)
else:
    Z0 = (120 * math.pi) / (math.sqrt(Er_eff) * (w_h + 1.393 + 0.667 * math.log(w_h + 1.444)))

print("Microstrip Impedance Calculator")
print("=" * 50)
print(f"Dielectric constant (Er): {Er}")
print(f"Dielectric height (h):    {h:.3f} mm")
print(f"Trace width (w):          {w:.3f} mm")
print(f"Copper thickness (t):     {t:.3f} mm")
print(f"\nEffective Er:             {Er_eff:.2f}")
print(f"Characteristic Z0:        {Z0:.1f} Ω")
print(f"\nTarget 50Ω: {'CLOSE' if abs(Z0 - 50) < 5 else 'ADJUST w or h'}")
print(f"Target 90Ω diff (~2×SE):  ~{2*Z0:.0f}Ω diff (with coupling)")

# Differential pair estimate
spacing = 0.15  # Gap between traces (mm)
Z_diff = 2 * Z0 * (1 - 0.48 * math.exp(-0.96 * spacing / h))
print(f"\nDiff pair (s={spacing}mm gap): {Z_diff:.1f} Ω")

Microstrip Impedance Calculator
==================================================
Dielectric constant (Er): 4.4
Dielectric height (h):    0.200 mm
Trace width (w):          0.150 mm
Copper thickness (t):     0.035 mm

Effective Er:             3.26
Characteristic Z0:        79.8 Ω

Target 50Ω: ADJUST w or h
Target 90Ω diff (~2×SE):  ~160Ω diff (with coupling)

Diff pair (s=0.15mm gap): 114.7 Ω

FPGA Integration

flowchart LR
    A["Sensors
ADC / SPI"] --> B["FPGA
Real-time DSP"]
    B --> C["MCU
Application
Logic"]
    C --> D["Connectivity
Wi-Fi / BLE"]
    B -->|"High-speed
parallel bus"| C
    E["Camera
MIPI CSI"] --> B
    F["Motor Control
PWM / Encoder"] --> B
                            

From FPGA to ASIC: The IC Design Flow

When an FPGA prototype proves the concept, production volumes may justify converting to an Application-Specific Integrated Circuit (ASIC). The IC design flow uses enterprise EDA tools from Synopsys, Cadence, and Siemens EDA — a different world from PCB-level KiCad and Altium, but one embedded engineers should understand when working with silicon vendors.

flowchart TD
    A["RTL Design\n(Verilog / VHDL)"] --> B["Synthesis\n(Synopsys Design Compiler,\nCadence Genus)"]
    B --> C["Gate-Level Netlist"]
    C --> D["Place & Route\n(Cadence Innovus)"]
    D --> E["Physical Verification\nDRC + LVS\n(Siemens Calibre,\nSynopsys IC Validator)"]
    E --> F["Timing Signoff\n(Synopsys PrimeTime)"]
    F --> G["GDSII Tapeout\n→ Foundry"]
    G --> H["Silicon Fabrication"]
                            

Hardware Security

Secure Boot & Tamper Protection

/* Secure boot chain verification concept
   Each stage verifies the next before executing */

#include <stdint.h>
#include <stdbool.h>

/* Simplified secure boot stages */
typedef struct {
    const char *name;
    uint32_t    load_addr;
    uint32_t    size;
    uint8_t     hash_sha256[32];  /* Expected SHA-256 hash */
    bool        signature_valid;
} boot_stage_t;

/* Boot chain: ROM → Bootloader → Firmware → App */
boot_stage_t boot_chain[] = {
    {"ROM Bootloader",  0x08000000, 16384,  {0}, true },  /* Immutable */
    {"2nd Stage BL",    0x08004000, 32768,  {0}, false},  /* Verify hash */
    {"Main Firmware",   0x0800C000, 262144, {0}, false},  /* Verify signature */
    {"Application",     0x08050000, 524288, {0}, false},  /* Verify signature */
};

/* Tamper detection GPIO configuration */
typedef struct {
    const char *description;
    uint8_t     gpio_pin;
    bool        active_low;    /* true = tamper when pin goes LOW */
    const char *response;
} tamper_input_t;

tamper_input_t tamper_inputs[] = {
    {"Enclosure open",   12, true,  "Erase keys, log event"},
    {"Mesh overlay",     14, true,  "Zeroize SRAM, halt"},
    {"Voltage glitch",   16, false, "Reset, increment counter"},
    {"Temperature alarm", 18, false, "Disable crypto, log"},
};

/* Security feature matrix */
/*
 * Feature              | SW Only | Secure Element | HSM
 * ---------------------|---------|----------------|-----
 * Key storage          | Flash   | ATECC608B      | TPM 2.0
 * Secure boot          | Hash    | ECDSA verify   | RSA/ECDSA
 * Random numbers       | PRNG    | True RNG       | FIPS RNG
 * Tamper response      | SW flag | Key zeroize    | Full wipe
 * Cost                 | $0      | $0.50-1.00     | $3-10
 * Certification        | None    | CC EAL4+       | FIPS 140-2
 */

Emerging Technologies

Interface Specification Tool

Practice Exercises

Series Conclusion

This 17-part series has taken you from fundamental electronics through schematic design, PCB layout, firmware integration, testing, production, and now advanced topics. The capstone projects that follow will give you hands-on experience combining these skills into complete, production-ready embedded systems.