USB Part 17: USB Hardware Design

USB-C Orientation & CC Pins

The USB-C connector contains 24 pins (12 per side, mirrored for reversibility). Understanding the CC1 and CC2 pins is essential for correct USB-C device design — they are the control signals that govern orientation detection, port role negotiation, and Power Delivery communication.

USB-C Pin Assignment Summary

The 24 pins are assigned as follows:

• VBUS (4 pins): A4, A9, B4, B9 — VBUS power supply, all connected together
• GND (4 pins): A1, A12, B1, B12 — ground
• D+/D- (4 pins): A6/A7 and B6/B7 — USB 2.0 differential data, both sets are connected together inside the connector (orientation-agnostic for USB 2.0)
• CC1, CC2 (2 pins): A5 (CC1), B5 (CC2) — configuration channel; only one is active depending on cable orientation
• VCONN (1 pin): Either CC1 or CC2 (whichever is not used for configuration) is used as VCONN to power active cable electronics (E-Marker chips)
• SSRX1+/- and SSTX1+/- (4 pins): SuperSpeed (USB 3.x) receive and transmit lanes for one orientation
• SSRX2+/- and SSTX2+/- (4 pins): SuperSpeed lanes for the opposite orientation (mux selects based on CC pin orientation detection)
• SBU1, SBU2 (2 pins): Sideband use pins — used for DisplayPort Alt Mode, Thunderbolt Alt Mode, and other alternate functions

CC Pin Pull Resistors for UFP (Device)

A USB-C UFP (Upstream-Facing Port — i.e., a device) must have Rd = 5.1 kΩ pull-down resistors on both CC1 and CC2. This is how the host (DFP — Downstream-Facing Port) detects that a device is connected and determines the current contract. When the host reads approximately 0.41 V on a CC pin (5 V VBUS through the host's Rp pull-up ÷ voltage divider with the device's 5.1 kΩ Rd), it recognizes a Default USB Current (900 mA for USB 3.x, 500 mA for USB 2.0) device.

/* ---------------------------------------------------------------
 * USB-C CC pin detection — read orientation from CC1/CC2
 * Used in a simple (non-PD) USB-C device implementation
 * The CC pin with the lower voltage (pulled toward GND by Rd)
 * is the active orientation line.
 * ---------------------------------------------------------------*/

/* ADC readings of CC1 and CC2 (0–3.3 V mapped to 0–4095 ADC counts) */
#define ADC_VBUS_THRESHOLD   409   /* ~0.33 V: CC pin connected to host */
#define ADC_OPEN_THRESHOLD  2048   /* ~1.65 V: CC pin floating / open   */

typedef enum {
    USB_C_ORIENTATION_UNKNOWN = 0,
    USB_C_ORIENTATION_CC1_ACTIVE,   /* Cable inserted: CC1 is the config channel */
    USB_C_ORIENTATION_CC2_ACTIVE,   /* Cable inserted: CC2 is the config channel */
} UsbC_Orientation_t;

UsbC_Orientation_t detect_usbc_orientation(uint16_t adc_cc1, uint16_t adc_cc2)
{
    bool cc1_connected = (adc_cc1 < ADC_OPEN_THRESHOLD);
    bool cc2_connected = (adc_cc2 < ADC_OPEN_THRESHOLD);

    if (cc1_connected && !cc2_connected) {
        return USB_C_ORIENTATION_CC1_ACTIVE;
    } else if (!cc1_connected && cc2_connected) {
        return USB_C_ORIENTATION_CC2_ACTIVE;
    } else if (cc1_connected && cc2_connected) {
        /* Both connected — active cable (VCONN cable) or PD negotiation in progress */
        /* For simple implementations, use the one with lower voltage as orientation */
        return (adc_cc1 < adc_cc2) ? USB_C_ORIENTATION_CC1_ACTIVE
                                    : USB_C_ORIENTATION_CC2_ACTIVE;
    }
    return USB_C_ORIENTATION_UNKNOWN;  /* No host connected */
}

Differential Pair Routing Rules

Differential pair routing for USB is not optional PCB artistry — it is an electrical specification. The USB 2.0 specification requires 90 Ω (±15%) differential impedance on D+/D- traces. Violating this requirement causes signal reflections, increased jitter, eye diagram violations, and ultimately enumeration failures or data corruption at high data rates.

Impedance Calculation

For edge-coupled microstrip differential pairs (traces on the outer PCB layer with a solid ground plane on the layer below), the differential impedance is determined by three parameters:

• Trace width (W): Wider trace = lower single-ended impedance
• Trace-to-trace spacing (S): Tighter spacing = more coupling = lower differential impedance
• Substrate height (H) and dielectric constant (ε_r): Standard FR4 has ε_r ≈ 4.3–4.6 at 12 MHz; at 480 MHz (HS) it is closer to 4.0 due to frequency dispersion

For a standard 1.6 mm FR4 4-layer PCB with 0.2 mm (8 mil) trace width and 0.2 mm (8 mil) gap on layer 1 with a ground plane on layer 2 at 0.2 mm substrate height, the differential impedance is approximately 90 Ω. Always verify the exact values with your PCB manufacturer's impedance calculator — they use your specific stackup measurements.

Routing Checklist

Crystal & Clock Requirements

USB Full Speed (12 Mbit/s) requires a precise 12 MHz (or 48 MHz) bit clock with a frequency tolerance of ±500 ppm at the operating temperature extremes. High Speed (480 Mbit/s) tightens this to ±500 ppm as well, but the absolute timing margins are far tighter because bit periods are 2.08 ns instead of 83.3 ns. Getting the clock wrong is a common source of enumeration failure, particularly on temperature extremes or over production unit variation.

Crystal Selection Parameters

Load Capacitor Calculation

The two load capacitors (C1, C2) connected to the crystal must be sized to present the crystal's rated load capacitance (C_L) when seen from the crystal's perspective. The formula is:

C_pcb = 2 × (C_L − C_stray)

Where C_stray is the sum of the oscillator circuit's input capacitance plus PCB parasitic capacitance (typically 3–5 pF total). For a 12 pF crystal with 4 pF stray: C_pcb = 2 × (12 − 4) = 16 pF. Use 15 pF or 18 pF standard values; the small residual mismatch results in a few ppm of frequency pull, well within the ±500 ppm budget.

HSI48 Internal RC (STM32L4/G0/G4) — No Crystal Needed

Many STM32 variants include a dedicated 48 MHz RC oscillator called HSI48, with a Clock Recovery System (CRS) peripheral that automatically trims the HSI48 frequency against the USB Start-of-Frame (SOF) packet received from the host every 1 ms. After a few seconds of enumeration, CRS typically achieves ±0.25% accuracy — well within USB requirements. This eliminates the cost, footprint, and assembly complexity of an external crystal entirely for Full Speed USB designs.

/* ---------------------------------------------------------------
 * STM32G0 / STM32L4 HSI48 + CRS configuration
 * No external crystal required for USB Full Speed
 * CRS trims HSI48 against USB SOF packets (1 kHz, 1 ms period)
 * ---------------------------------------------------------------*/

void SystemClock_Config_HSI48_USB(void)
{
    RCC_OscInitTypeDef RCC_OscInit = {0};
    RCC_ClkInitTypeDef RCC_ClkInit = {0};
    RCC_CRSInitTypeDef RCC_CRSInit = {0};

    /* Enable HSI48 oscillator */
    RCC_OscInit.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
    RCC_OscInit.HSI48State     = RCC_HSI48_ON;
    RCC_OscInit.PLL.PLLState   = RCC_PLL_NONE;
    HAL_RCC_OscConfig(&RCC_OscInit);

    /* Select HSI48 as USB clock source */
    RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
    PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

    /* Configure CRS — Clock Recovery System
     * Source: USB SOF (Start of Frame), 1 kHz
     * Target: 48 MHz HSI48
     * USB SOF arrives every 1000 µs, providing a precise reference */
    RCC_CRSInit.Prescaler    = RCC_CRS_SYNC_DIV1;
    RCC_CRSInit.Source       = RCC_CRS_SYNC_SOURCE_USB;
    RCC_CRSInit.Polarity     = RCC_CRS_SYNC_POLARITY_RISING;
    RCC_CRSInit.ReloadValue  = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
    RCC_CRSInit.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;  /* ±34 ppm window */
    RCC_CRSInit.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
    HAL_RCCEx_CRSConfig(&RCC_CRSInit);

    /* Set system clock to HSI48 */
    RCC_ClkInit.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
                            RCC_CLOCKTYPE_PCLK1  | RCC_CLOCKTYPE_PCLK2;
    RCC_ClkInit.SYSCLKSource   = RCC_SYSCLKSOURCE_HSI48;
    RCC_ClkInit.AHBCLKDivider  = RCC_SYSCLK_DIV1;
    RCC_ClkInit.APB1CLKDivider = RCC_HCLK_DIV1;
    RCC_ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
    HAL_RCC_ClockConfig(&RCC_ClkInit, FLASH_LATENCY_2);
}

ESD & Overvoltage Protection

ESD (Electrostatic Discharge) is the most common cause of USB hardware damage in production and field use. The human body model (HBM) ESD test applies a 2 kV to 8 kV pulse to the USB connector pins — a realistic simulation of a user touching the connector after walking across a carpet. Without protection, this pulse destroys the USB controller's input stage on the MCU. IEC 61000-4-2, the standard ESD immunity specification, requires the device to survive ±8 kV contact discharge without damage or malfunction.

TVS Diode Selection

The key parameter for USB ESD protection is junction capacitance (C_io). Every picofarad of capacitance added to D+ or D- degrades signal integrity at high data rates. For USB 2.0 Full Speed (12 Mbit/s), components up to 2–3 pF per line are acceptable. For High Speed (480 Mbit/s), capacitance must be below 0.5 pF per line — a very tight constraint that eliminates many otherwise suitable TVS devices.

Complete VBUS Protection Schematic

A complete VBUS protection circuit for a bus-powered USB device consists of the following components, placed in order from the connector outward to the rest of the circuit:

1. J1 (USB-C Connector): VBUS pins (A4, A9, B4, B9) — all four VBUS pins shorted together at the connector.
2. F1 (Polyfuse on VBUS): 500 mA PPTC resettable fuse (e.g., Bourns MF-MSMF050-2) in series with VBUS. Nominal resistance 0.4 Ω, trips at 1.0 A. Limits current available to the charge pump in a USB Killer attack and protects downstream circuitry from host overcurrent.
3. D1 (VBUS TVS): 5.1 V unidirectional TVS diode (e.g., SMBJ5.0A) from VBUS to GND, placed after the polyfuse. Clamps any overvoltage transients — power supply glitches, cable inrush pulses — to a safe level before they reach the input capacitors.
4. C1 (Bulk decoupling): 4.7 µF / 10 V X5R ceramic capacitor on VBUS to GND. Provides bulk charge for inrush demand and filters low-frequency supply noise.
5. C2 (High-frequency decoupling): 100 nF / 10 V X7R ceramic capacitor on VBUS to GND, placed close to the MCU VBUS pin. Filters high-frequency switching noise.
6. D2 (ESD on D+/D-): PRTR5V0U2X (or PRTR5V0U2XS for HS) TVS array, placed within 1–2 mm of the USB connector body. Protects D+ and D- from ESD pulses. Connected between D+ and GND, and D- and GND, with a common VBUS pin for clamp reference.
7. FB1 (Ferrite bead on VBUS): 600 Ω @ 100 MHz ferrite bead (e.g., Murata BLM18AG601SN1D) in series with VBUS before C1. Attenuates high-frequency noise conducted from the host or cable onto VBUS. Select a bead rated for the maximum expected current (at least 600 mA for USB 2.0 default current).

VBUS Detection & Power Path

A bus-powered USB device should not assert the D+ pull-up resistor until VBUS is confirmed to be within specification (4.75–5.25 V). Asserting D+ without a valid VBUS causes partial enumeration attempts, confusion in some hosts, and wastes power trying to communicate on a dead bus. Detecting VBUS via a GPIO-connected voltage divider and gating the D+ pull-up on software is the correct approach.

VBUS Detection Voltage Divider

VBUS is 5 V; most MCU GPIO inputs are limited to 3.3 V maximum. A two-resistor voltage divider scales VBUS to a GPIO-safe level. Recommended values: R_top = 100 kΩ, R_bot = 100 kΩ (for a 2:1 divider giving 2.5 V from 5 V VBUS). The input impedance is 50 kΩ — high enough to not significantly load VBUS, low enough to pull the GPIO low quickly when VBUS is removed. For 3.3 V MCUs: any divider giving ≤ 3.0 V from 5.25 V (worst case max VBUS) is acceptable.

/* ---------------------------------------------------------------
 * VBUS detection and D+ pull-up gating
 * Enable USB connection only when VBUS is confirmed present
 * ---------------------------------------------------------------*/

#define VBUS_DETECT_GPIO_PORT   GPIOA
#define VBUS_DETECT_GPIO_PIN    GPIO_PIN_9   /* PA9 via voltage divider */
#define VBUS_THRESHOLD_ADC      2048U        /* ~1.65 V: VBUS > ~3.3 V */

/* TinyUSB remote wakeup / connect callback — called by main task */
void usb_vbus_task(void)
{
    static bool usb_connected = false;
    bool vbus_present;

    /* Read VBUS level — GPIO configured as analog or digital input */
    uint32_t adc_val = ADC_ReadChannel(ADC1, ADC_CHANNEL_9);
    vbus_present = (adc_val > VBUS_THRESHOLD_ADC);

    if (vbus_present && !usb_connected) {
        /* VBUS just appeared — enable USB peripheral and D+ pull-up */
        usb_connected = true;
        board_usb_connect();    /* Enable internal or external pull-up */
        TU_LOG1("VBUS detected — USB connecting\r\n");
    } else if (!vbus_present && usb_connected) {
        /* VBUS removed — disable USB, release D+ */
        usb_connected = false;
        board_usb_disconnect();  /* Disable pull-up and USB peripheral */
        TU_LOG1("VBUS lost — USB disconnected\r\n");
    }
}

Inrush Current Limiting with a Power Path Switch

When a USB device is first plugged in, the bulk capacitance on the device's internal power rails must be charged from VBUS. If the capacitance is large (hundreds of µF, common in designs with significant bulk energy storage), the inrush current spike can exceed the USB specification's 50 µC limit, causing the host's current-limit circuitry to trip and preventing enumeration.

A power path switch IC solves this elegantly. The TI TPS2552 (500 mA) and TI TPS2553 (1 A) are purpose-designed USB power path switches that provide:

• Inrush current limiting: Controlled slew-rate on the output voltage, limiting dV/dt and thus i = C × dV/dt to a safe level
• Overcurrent protection: Electronically latches off if current exceeds the set threshold (500 mA or 1 A)
• Enable control: The EN pin allows firmware to disconnect load entirely during USB suspend for sub-2.5 mA suspend current compliance
• Fault flag output: Open-drain /FAULT pin signals overcurrent events to the MCU for logging or error handling

Self-powered devices (devices that have their own power supply and do not draw from VBUS for their main operation) must still not draw more than 100 mA from VBUS even in an unconfigured state. Use a power path switch with a 100 mA current limit between VBUS and any circuitry that might draw from VBUS while unconfigured.

USB Hub Design

Designing a USB hub is a common requirement in multi-port industrial controllers, docking stations, embedded test equipment, and IoT gateways. A USB hub connects one upstream port (to the host) to multiple downstream ports (to devices), handling bus topology, transaction translation, and power distribution.

Transaction Translator (TT) Architecture

Full Speed and Low Speed devices connected to a High Speed hub require a Transaction Translator (TT) — a bridge inside the hub that converts HS transactions (480 Mbit/s) from the host to FS/LS transactions (12/1.5 Mbit/s) on the downstream port. There are two TT architectures:

• Single TT: All downstream ports share one TT. Total FS/LS bandwidth is limited to approximately 7–10 Mbit/s aggregate across all ports. Suitable for hubs where only one or two FS devices will be active simultaneously.
• Multiple TT (MTT): Each downstream port has its own dedicated TT. Full FS bandwidth (12 Mbit/s) is available on each port independently. Required for applications where multiple FS devices need simultaneous full bandwidth (e.g., 4 CDC serial ports at full speed simultaneously).

SMSC USB2514B — 4-Port High Speed Hub

The Microchip (formerly SMSC) USB2514B is a 4-port High Speed USB hub controller IC with Multiple TT architecture, I2C configuration interface, and per-port VBUS switching control. It is one of the most widely used hub controllers in industrial embedded designs.

Key design requirements for the USB2514B reference schematic:

• Crystal: 25 MHz ±50 ppm, 12 pF load capacitance. The USB2514B uses an internal PLL to generate the 480 MHz HS reference from the 25 MHz crystal. A 25 MHz crystal is required — the part does not have an internal RC oscillator. Suitable crystal: TXC 7M-25.000MAAJ-T (7×5 mm SMD, ±50 ppm, AEC-Q200 qualified).
• VBUS switching per port: Each downstream port's VBUS is controlled by a dedicated GPIO from the USB2514B (PRTPWR1–4 open-drain outputs). Connect each PRTPWR pin to the enable input of a per-port power switch IC (e.g., Microchip MIC2026 dual-channel) with a 500 mA current limit per port.
• I2C configuration: The USB2514B reads its VID, PID, string descriptors, and port power configuration from an external 24LC02B I2C EEPROM at startup. This allows customizing hub identity without changing firmware. Connect to MCU I2C bus for in-system EEPROM programming during manufacturing.
• EMI filtering on downstream ports: Place a common-mode choke (e.g., TDK ACM2012-900-2P-T002) on each downstream port's D+/D- pair. This attenuates common-mode noise generated by downstream devices from appearing on the upstream bus.
• RESET# pin: Assert low for at least 1 µs after power supply ramp. Control via MCU GPIO to allow software reset of the hub if a port hangs.
• VDDA and VDDD decoupling: Place 100 nF + 1 µF decoupling on every VDD and VDDA pin, as close to the IC as possible. The USB2514B has separate analog and digital power supplies — both must be well decoupled.

PCB Stackup & Layer Assignment

The PCB stackup — the number of copper layers, their order, and the dielectric materials between them — is a fundamental design decision that affects impedance control, EMI performance, and manufacturing cost. For USB designs, a 4-layer PCB is the minimum recommended stackup for any Full Speed or High Speed design. 2-layer PCBs can work for very simple Low Speed USB peripherals but make impedance-controlled routing extremely difficult.

Recommended 4-Layer Stackup for USB

Component Placement Rules

PCB component placement should follow a functional clustering approach for USB designs:

• USB connector area: Place ESD protection ICs (PRTR5V0U2X), VBUS polyfuse, and VBUS TVS diode within 2 mm of the connector pins. Route the "dirty" (pre-protection) traces only in this small area. All traces leaving the connector area to the rest of the board should be the "clean" (post-protection) signals.
• Crystal circuit: Place the crystal and load capacitors within 3 mm of the MCU's OSC_IN and OSC_OUT pins. Surround with a ground pour connected to the crystal's case pad and the PCB chassis GND. Keep high-frequency switching signals at least 10 mm away from the crystal.
• VBUS decoupling: Place the bulk capacitor (4.7 µF) and the ferrite bead on VBUS close together, with the ferrite bead closer to the connector and the capacitor on the MCU side. The 100 nF decoupling capacitors must be within 0.5 mm of their respective MCU power pins.
• Hub controller (if used): Place the USB2514B centrally among its upstream and downstream connectors to equalize trace lengths. All downstream port D+/D- pairs should be length-matched to within ±5 mil of each other as well as internally matched.

Ground Stitching Vias

The USB connector's metallic shield should be connected to the PCB ground plane through multiple vias (minimum 4, ideally 6–8) placed at the corners and midpoints of the connector footprint. This stitches the connector's Faraday cage effect into the PCB ground plane, significantly reducing radiated emissions from the connector area. Add additional GND stitching vias on both sides of the USB differential pair traces, spaced at approximately every half wavelength of the highest frequency of interest (for HS USB: λ/2 at 480 MHz ≈ 160 mm in FR4, so spacing of 20–40 mm is more than adequate).

EMC & Compliance Considerations

USB devices sold in the EU must meet CE marking requirements, which for USB electronics primarily means compliance with the EMC Directive (2014/30/EU). In the USA and Canada, FCC Part 15 Class B (for consumer products) applies. These regulations limit radiated and conducted electromagnetic emissions to levels that prevent interference with radio communications. USB is a notoriously difficult interface to keep within EMC limits due to its fast edge rates (0.4–4 ns rise times for FS USB).

Common Mode Choke

A common mode choke on the D+ and D- lines is one of the most effective EMC measures available to the hardware designer. Unlike the differential impedance (which carries the useful signal), common-mode chokes attenuate common-mode noise — noise that appears equally on both D+ and D- relative to ground, often from board-level switching regulators or MCU core switching currents coupling into the USB lines.

Recommended part: TDK ACM2012-900-2P-T002 — 90 Ω common-mode impedance at 100 MHz, 0.5 A rated, 0.3 pF differential capacitance (safe for HS USB). Place it in series with D+/D- between the ESD protection IC and the MCU's USB pins. The common-mode choke significantly attenuates 30–300 MHz radiated emissions without affecting the 12 MHz or 480 MHz differential signal.

Ferrite Bead on VBUS

The ferrite bead on VBUS (described in Section 5) also serves an EMC function: it prevents high-frequency switching noise from the device's internal power supply from being conducted back onto the VBUS line and out through the cable as conducted emissions. Select a ferrite bead with high impedance at 100 MHz (minimum 200 Ω, ideally 600 Ω) and sufficient current rating for the device's maximum VBUS current draw.

USB-IF Certification

Products that bear the USB trident logo must be certified by the USB Implementers Forum. Certification requires:

• USB-IF Membership: Annual fee (currently ~$6,000/year for non-affiliate members). Membership grants access to the USB-IF compliance test specification documents and the test event list.
• Vendor ID (VID) allocation: Included with USB-IF membership. Your product's VID/PID pair must be registered.
• Compliance testing at a USB-IF authorized test lab: The device undergoes electrical compliance (eye diagram, signal quality, descriptor validation), interoperability testing with USB-IF reference hosts and devices, and USB Power Delivery compliance if applicable.
• USB Logo License: After passing compliance testing, a logo license is required to use the USB trident logo on the product.

For prototypes and internal products, formal USB-IF certification is not required. However, performing pre-compliance testing before the full compliance submission saves significant money in test failures and redesign cycles. Pre-compliance testing involves:

• Radiated emissions measurement in a semi-anechoic chamber or OATS (Open Area Test Site) with a 1 m antenna, confirming emissions are below FCC/CE limits at 10 dB margin (accounting for measurement uncertainty)
• Conducted emissions on VBUS using a LISN (Line Impedance Stabilization Network) and spectrum analyser
• ESD gun test per IEC 61000-4-2 (±2 kV air, ±4 kV contact discharge) applied to all accessible connectors

Complete Hardware Design Checklist

This checklist covers the complete set of hardware design requirements for a production-quality USB device. Each item should be verified before sending the design to manufacturing and again after receiving the first prototype batch.

Series Complete — What Next?

You have reached the end of the USB Development Mastery series. Across 17 parts, we have built a complete mental model of USB from physical electrons to production-ready hardware and firmware:

• Parts 1–3: USB system architecture, differential signaling, J/K/SE0 states, VBUS management, the nine-step enumeration sequence, descriptor hierarchy, packet structure.
• Parts 4–9: All major USB device classes in depth — HID (keyboards, mice, gamepads), CDC (virtual COM port), MSC (mass storage), and composite devices combining multiple classes.
• Parts 5: TinyUSB internals — the task model, porting layer, USB buffer pool, descriptor configuration macros, and callback architecture.
• Parts 10–12: Advanced debugging with Wireshark and protocol analysers, RTOS integration patterns (FreeRTOS + TinyUSB), and advanced topics including alternate settings, isochronous transfers, and vendor-defined class drivers.
• Parts 13–15: Performance optimization for bulk transfers, custom class driver development from scratch, and bare-metal register-level USB programming on STM32.
• Part 16: USB security — BadUSB, USB Killer, descriptor fuzzing, signed DFU with ECDSA P-256, firmware encryption, RDP protection, and host input validation.
• Part 17: Production USB hardware design — connector selection, impedance routing, crystal design, ESD circuits, hub design, PCB stackup, and EMC compliance.

Suggested Project Ideas

Now that you have the complete foundation, here are four capstone project ideas that apply multiple parts of the series together:

• USB Data Logger: A composite USB device (CDC + MSC) built on an STM32L4 or RP2040. CDC provides real-time data streaming to a PC terminal; MSC exposes the onboard SPI flash as a USB drive for CSV log download. Requires Parts 6 (CDC), 8 (MSC), 9 (Composite), and 17 (hardware design) applied together.
• USB HID Controller: A custom game controller or input device using the HID custom descriptor approach from Part 7. Challenge: support all button, axis, and rumble output report features, with a properly formatted HID report descriptor that passes the USB-IF HID descriptor parser validation tool.
• USB CDC-to-CAN Bridge: A CDC virtual COM port device that bridges USB serial to a CAN bus using an onboard CAN controller (e.g., MCP2515 over SPI). Host sends ASCII CAN frame strings; device transmits them on the CAN bus and relays received CAN frames back to the host. Demonstrates real industrial bridge applications for the CDC class.
• USB Audio Interface: A USB Audio Class 1.0 device (isochronous transfers, Part 12) that connects a stereo audio codec to USB. The host streams 48 kHz / 16-bit PCM audio to the device, which outputs to a headphone jack. Challenge: isochronous feedback endpoints for sample rate synchronization. This is the hardest project in the list and demonstrates full mastery of the series.

Community and Further Resources

The USB development community is active and welcoming. Key resources for continued learning:

• TinyUSB GitHub: https://github.com/hathach/tinyusb — The reference implementation for everything covered in this series. Study the examples (device/device_cdc_msc, device/hid_generic_inout, device/audio_4_channel_mic) alongside the corresponding articles in this series.
• USB-IF Specification Documents: https://usb.org/documents — The authoritative source for all USB specifications. The USB 2.0 specification, USB 3.2 specification, USB Type-C specification, and USB Power Delivery specification are all freely available in PDF form.
• USB Made Simple: http://www.usbmadesimple.co.uk — An excellent reference website with detailed descriptions of each USB transaction type, descriptor structure, and class protocol.
• BeyondLogic USB in a Nutshell: https://www.beyondlogic.org/usbnutshell/usb1.shtml — The classic introductory USB reference that many embedded engineers have bookmarked since the early 2000s. Still accurate and extremely clearly written.
• EEVBlog and Sigrok forums: Active communities for hardware debugging and protocol analysis questions.

Practical Exercises

These exercises apply the hardware design concepts from this article to real PCB design work. The final exercise is the capstone challenge for the entire series.

USB Hardware Design Document Generator

Use this tool to document your USB hardware design — connector type, MCU, speed, PCB layers, ESD and polyfuse decisions, crystal selection, and design notes. Download as Word, Excel, PDF, or PowerPoint for design review, manufacturing handoff, or compliance documentation.

Conclusion — The End of the Journey

We have reached the end. In this final part we covered everything needed to take a USB design from schematic to production-ready hardware:

• Connector selection — USB-C is the right choice for all new designs. Its reversible orientation, 10,000-cycle mechanical rating, and power delivery capability make all other connector types legacy choices.
• CC pin design — 5.1 kΩ pull-down resistors on both CC1 and CC2 are mandatory for any USB-C device. Missing these prevents VBUS from being enabled on many hosts. Orientation detection via ADC reading of CC pins allows firmware to configure the SuperSpeed mux if USB 3.x is implemented.
• Differential pair routing — 90 Ω differential impedance, ±5 mil length matching, no traces between D+ and D-, solid GND reference plane below, no vias unless symmetric. These rules are specification mandates, not suggestions.
• Crystal design — total frequency error budget ≤ ±500 ppm, load capacitors sized with the formula C_pcb = 2 × (C_L − C_stray). For Full Speed designs on STM32, HSI48 with CRS eliminates the crystal entirely and is highly recommended.
• ESD and VBUS protection — PRTR5V0U2X (or PRTR5V0U2XS for HS) for D+/D- protection, MF-MSMF050 polyfuse and SMBJ5.0A TVS for VBUS. All protection must be placed before the traces branch into the rest of the PCB.
• VBUS detection — voltage divider to GPIO prevents enumeration attempts on a dead bus and enables proper USB suspend power management.
• USB hub design — USB2514B 4-port hub with 25 MHz crystal, I2C EEPROM configuration, per-port power switching, and common-mode chokes on downstream ports.
• 4-layer PCB stackup — L1 signal / L2 solid GND / L3 power / L4 signal is the standard for USB designs. Component placement in functional clusters near the connector minimizes trace length and EMI loop area.
• EMC compliance — common-mode choke on D+/D-, ferrite bead on VBUS, shielded connector, pre-compliance emissions testing before formal submission. USB-IF certification requires membership and formal test lab testing.

More than any individual technical fact in this series, I hope the overarching lesson is this: USB is a complete system. The physical electrons on D+ and D-, the firmware running your descriptor parser, the security properties of your DFU bootloader, and the impedance of your PCB traces are all part of one coherent whole. A failure at any level — an unprotected ESD event, a malformed descriptor, an unsigned firmware image, a mis-routed differential pair — can make the difference between a product that ships and one that doesn't.

Thank you for reading all 17 parts of the USB Development Mastery series. I hope it has given you the confidence to design, build, and ship USB devices that are reliable, secure, and production-ready. Now plug something in. Make it enumerate. Make it count.