CMSIS Part 6: CMSIS-DSP — Filters, FFT & Math Functions

CMSIS-DSP Library Architecture

CMSIS-DSP is a compiled library — not header-only like CMSIS-Core. It ships as a pre-built static library (libarm_cortexM4lf_math.a for Cortex-M4 with FPU, for example) and as source that you can compile yourself with the exact flags matching your target. The single include is arm_math.h, which pulls in type definitions, function declarations, and the instance structs that CMSIS-DSP algorithms use to hold their persistent state.

The instance struct model is central to CMSIS-DSP design. Stateful algorithms (FIR, IIR, FFT) keep their internal state — delay line, twiddle factors, coefficient array — in a struct that you allocate in your application and pass to every function call. This eliminates hidden global state and makes it trivial to run multiple independent filter instances simultaneously, each with its own state buffer.

# Add CMSIS-DSP to a CMake project using the CMSIS-DSP source tree
# (CMSIS-DSP 1.15+ supports CMake natively via add_subdirectory)

# In CMakeLists.txt:
# set(DISABLEFLOAT16 ON)   # disable fp16 if not needed
# add_subdirectory(CMSIS-DSP/Source CMSISDSPBinary)
# target_link_libraries(my_firmware PRIVATE CMSISDSP)
# target_compile_definitions(my_firmware PRIVATE ARM_MATH_CM4 __FPU_PRESENT=1)

# Or link the pre-built library for Cortex-M4F hard-float ABI:
# target_link_libraries(my_firmware PRIVATE
#     ${CMSIS_DSP_LIB_DIR}/libarm_cortexM4lf_math.a)

# Verify the library exports the expected symbols
arm-none-eabi-nm libarm_cortexM4lf_math.a | grep arm_fir_init_f32

FIR Filters

A Finite Impulse Response (FIR) filter computes each output sample as a weighted sum of the current and previous N-1 input samples, where N is the filter order (tap count). FIR filters are inherently stable (no feedback), can achieve exactly linear phase (vital for audio and communications), and map directly to the multiply-accumulate hardware available in Cortex-M4/M7 DSP extensions.

The standard design workflow: (1) specify the filter in the frequency domain (passband, stopband, transition width, attenuation); (2) compute coefficients using a windowed sinc method (Hamming window for audio, Kaiser window for tighter specifications); (3) pass the coefficients and state buffer to arm_fir_init_f32(); (4) call arm_fir_f32() once per block of samples.

/* ── fir_audio_lowpass.c ─────────────────────────────────────────────────
 * 64-tap FIR low-pass filter for audio at 48 kHz sample rate.
 * Cut-off: 8 kHz. Designed with Hamming window (windowed sinc).
 * Coefficients generated by SciPy: scipy.signal.firwin(64, 8000/24000)
 * ──────────────────────────────────────────────────────────────────────── */
#include "arm_math.h"

#define BLOCK_SIZE  64U   /* samples processed per call — match DMA buffer  */
#define NUM_TAPS    64U   /* filter order + 1                                 */

/* FIR coefficients (symmetric, Hamming-windowed sinc, fc = 8 kHz @ 48 kHz) */
static const float32_t g_fir_coeffs[NUM_TAPS] = {
    /* Generated offline; symmetric so only half shown here, padded to 64 */
     0.00000f,  0.00019f, -0.00048f, -0.00063f,  0.00000f,  0.00159f,
     0.00247f,  0.00000f, -0.00489f, -0.00647f,  0.00000f,  0.01103f,
     0.01371f,  0.00000f, -0.02221f, -0.02756f,  0.00000f,  0.05011f,
     0.07568f,  0.09003f,  0.09003f,  0.07568f,  0.05011f,  0.00000f,
    -0.02756f, -0.02221f,  0.00000f,  0.01371f,  0.01103f,  0.00000f,
    -0.00647f, -0.00489f,  0.00000f,  0.00247f,  0.00159f,  0.00000f,
    -0.00063f, -0.00048f,  0.00019f,  0.00000f,  0.00000f,  0.00000f,
     0.00000f,  0.00000f,  0.00000f,  0.00000f,  0.00000f,  0.00000f,
     0.00000f,  0.00000f,  0.00000f,  0.00000f,  0.00000f,  0.00000f,
     0.00000f,  0.00000f,  0.00000f,  0.00000f,  0.00000f,  0.00000f,
     0.00000f,  0.00000f,  0.00000f,  0.00000f
};

/* State buffer: NUM_TAPS + BLOCK_SIZE - 1 elements */
static float32_t g_fir_state[NUM_TAPS + BLOCK_SIZE - 1U];

/* Instance struct — holds pointers to coefficients and state */
static arm_fir_instance_f32 g_fir;

/* ── One-time initialisation ─────────────────────────────────────────── */
void fir_init(void)
{
    arm_fir_init_f32(
        &g_fir,         /* instance struct (persistent state)  */
        NUM_TAPS,       /* number of filter taps               */
        g_fir_coeffs,   /* pointer to coefficient array        */
        g_fir_state,    /* pointer to state buffer             */
        BLOCK_SIZE);    /* block size for block processing     */
}

/* ── Called every DMA interrupt or RTOS block tick ──────────────────── */
void fir_process(float32_t *p_input, float32_t *p_output)
{
    /* Process BLOCK_SIZE samples in a single vectorised call.
     * On Cortex-M4F the inner loop uses SIMD MAC instructions,
     * achieving ~4 MACs per cycle vs 1 in scalar code.             */
    arm_fir_f32(&g_fir, p_input, p_output, BLOCK_SIZE);
}

IIR Biquad Filters

Where FIR filters require many taps to achieve steep roll-off, Infinite Impulse Response (IIR) filters achieve the same response with far fewer coefficients by using feedback. The trade-off: IIR filters can be unstable if poorly implemented, and they introduce non-linear phase shift. For most sensor and audio applications these are acceptable trade-offs — a 4-stage biquad cascade achieves an 8th-order Butterworth response with only 20 coefficients.

CMSIS-DSP implements the biquad in Direct Form II Transposed (arm_biquad_cascade_df2T_f32), which has superior numerical properties compared to Direct Form I — it requires fewer delay elements and is less prone to coefficient quantisation noise. Each stage has five coefficients: b0, b1, b2 (feedforward), a1, a2 (feedback), stored in the order [b0, b1, b2, a1, a2].

/* ── iir_biquad_dc_removal.c ─────────────────────────────────────────────
 * Two-stage biquad cascade for DC removal from a sensor signal.
 * Stage 1: High-pass 1 Hz (removes DC offset and slow drift).
 * Stage 2: Notch at 50 Hz (removes mains interference).
 * Coefficients for 1 kHz sample rate, computed with scipy.signal.
 * ──────────────────────────────────────────────────────────────────────── */
#include "arm_math.h"

#define NUM_STAGES  2U   /* cascade of 2 biquad sections */

/* Coefficients in DF2T order: [b0, b1, b2, a1, a2] per stage
 * Negative a-coefficients because CMSIS-DSP sign convention flips them. */
static float32_t g_biquad_coeffs[5U * NUM_STAGES] = {
    /* Stage 1 — 1 Hz high-pass (fc=1 Hz, Q=0.707, fs=1000 Hz) */
     0.99368f, -1.98736f,  0.99368f,  /* b0, b1, b2 */
     1.98728f, -0.98744f,             /* a1, a2 (CMSIS sign: stored positive) */
    /* Stage 2 — 50 Hz notch (fs=1000 Hz, bandwidth=5 Hz) */
     0.97204f, -1.90211f,  0.97204f,  /* b0, b1, b2 */
     1.90211f, -0.94408f              /* a1, a2 */
};

/* State buffer: 2 elements per stage */
static float32_t g_biquad_state[2U * NUM_STAGES];

/* Instance struct */
static arm_biquad_cascade_df2T_instance_f32 g_biquad;

void biquad_init(void)
{
    arm_biquad_cascade_df2T_init_f32(
        &g_biquad,
        NUM_STAGES,
        g_biquad_coeffs,
        g_biquad_state);
}

void biquad_process(float32_t *p_src, float32_t *p_dst, uint32_t block_size)
{
    arm_biquad_cascade_df2T_f32(&g_biquad, p_src, p_dst, block_size);
}

FFT & Spectral Analysis

The Fast Fourier Transform converts a block of time-domain samples into a frequency-domain magnitude spectrum. For embedded systems, the most common application is identifying dominant frequencies in a vibration, acoustic, or physiological signal — without knowing in advance what those frequencies are. CMSIS-DSP provides arm_rfft_fast_f32() for real-valued input at half the computational cost of a full complex FFT.

The output of the RFFT for N input samples is N/2 complex pairs (N floats total): bin 0 is the DC component, bin 1 corresponds to frequency fs/N Hz, bin k corresponds to frequency k*fs/N Hz, up to the Nyquist frequency at bin N/2. Use arm_cmplx_mag_f32() to compute magnitudes and arm_max_f32() to find the peak bin.

/* ── fft_vibration_analysis.c ────────────────────────────────────────────
 * Real FFT for vibration spectrum analysis on accelerometer data.
 * FFT size: 1024 samples. Sample rate: 10 kHz.
 * Frequency resolution: 10000/1024 ≈ 9.77 Hz per bin.
 * ──────────────────────────────────────────────────────────────────────── */
#include "arm_math.h"
#include 

#define FFT_SIZE    1024U
#define SAMPLE_RATE 10000.0f   /* Hz */

/* Hann window coefficients (computed offline, stored in flash) */
static const float32_t g_hann_window[FFT_SIZE] = {
    /* w[n] = 0.5 * (1 - cos(2*pi*n/(N-1))) for n = 0..N-1 */
    /* Abbreviated — full 1024-element array in production code */
    0.0f, /* [0]   */
    /* ... */
};

/* Input buffer and FFT output buffer */
static float32_t g_input_buf[FFT_SIZE];    /* windowed time-domain samples  */
static float32_t g_fft_output[FFT_SIZE];   /* complex output (N floats)     */
static float32_t g_magnitude[FFT_SIZE/2U]; /* magnitude spectrum            */

/* RFFT instance struct */
static arm_rfft_fast_instance_f32 g_rfft;

void fft_init(void)
{
    /* Initialise for FFT_SIZE-point transform */
    arm_rfft_fast_init_f32(&g_rfft, FFT_SIZE);
}

float32_t fft_find_peak_frequency(const float32_t *p_accel_samples)
{
    /* Step 1: Apply Hann window to reduce spectral leakage */
    arm_mult_f32(p_accel_samples, g_hann_window, g_input_buf, FFT_SIZE);

    /* Step 2: Compute real FFT (forward transform, ifftFlag = 0) */
    arm_rfft_fast_f32(&g_rfft, g_input_buf, g_fft_output,
                      0U /* ifftFlag=0 for forward FFT */);

    /* Step 3: Compute magnitude of each complex bin
     * g_fft_output layout: [Re0, Re_N/2, Re1, Im1, Re2, Im2, ...] */
    /* Skip bin 0 (DC) and bin N/2 (Nyquist) — start from index 2 */
    arm_cmplx_mag_f32(&g_fft_output[2], &g_magnitude[1],
                      (FFT_SIZE / 2U) - 1U);

    /* Step 4: Find the bin with the maximum magnitude */
    float32_t max_val;
    uint32_t  max_idx;
    arm_max_f32(&g_magnitude[1], (FFT_SIZE / 2U) - 1U,
                &max_val, &max_idx);
    max_idx += 1U; /* adjust for skipped DC bin */

    /* Step 5: Convert bin index to frequency in Hz */
    float32_t peak_freq_hz = (float32_t)max_idx * SAMPLE_RATE / (float32_t)FFT_SIZE;

    return peak_freq_hz;
}

Performance Optimisation

CMSIS-DSP's hand-optimised code uses ARMv7E-M SIMD intrinsics (such as __SMLAD, __PKHBT) to pack two 16-bit operations into one 32-bit instruction on Cortex-M4/M7. This gives 2–4x speedup over equivalent scalar C. On Cortex-M55 and M85 with the M-Profile Vector Extension (MVE / Helium), CMSIS-DSP 1.10+ uses 128-bit SIMD lanes for up to 8x throughput on Q15 operations.

/* ── perf_comparison.c ───────────────────────────────────────────────────
 * Compare Q15 vs float32 FIR performance using DWT cycle counter.
 * Run on Cortex-M4F at 168 MHz (STM32F407).
 * ──────────────────────────────────────────────────────────────────────── */
#include "arm_math.h"
#include "core_cm4.h"  /* for DWT_CYCCNT */
#include 
#include 

#define TAPS       64U
#define BLOCK      256U

/* Enable DWT cycle counter (one-time setup) */
static void dwt_enable(void)
{
    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
    DWT->CYCCNT  = 0U;
    DWT->CTRL   |= DWT_CTRL_CYCCNTENA_Msk;
}

static uint32_t dwt_cycles(void) { return DWT->CYCCNT; }

static float32_t  g_f32_coeffs[TAPS];
static float32_t  g_f32_state[TAPS + BLOCK - 1U];
static float32_t  g_f32_in[BLOCK], g_f32_out[BLOCK];
static arm_fir_instance_f32 g_f32_fir;

static q15_t g_q15_coeffs[TAPS];
static q15_t g_q15_state[TAPS + BLOCK - 1U];
static q15_t g_q15_in[BLOCK], g_q15_out[BLOCK];
static arm_fir_instance_q15 g_q15_fir;

void perf_compare(void)
{
    dwt_enable();

    arm_fir_init_f32(&g_f32_fir, TAPS, g_f32_coeffs, g_f32_state, BLOCK);
    arm_fir_init_q15(&g_q15_fir, TAPS, g_q15_coeffs, g_q15_state, BLOCK);

    /* Benchmark float32 FIR */
    uint32_t t0 = dwt_cycles();
    arm_fir_f32(&g_f32_fir, g_f32_in, g_f32_out, BLOCK);
    uint32_t f32_cycles = dwt_cycles() - t0;

    /* Benchmark Q15 FIR */
    t0 = dwt_cycles();
    arm_fir_fast_q15(&g_q15_fir, g_q15_in, g_q15_out, BLOCK);
    uint32_t q15_cycles = dwt_cycles() - t0;

    /* Typical results on STM32F407 @ 168 MHz, 64-tap, 256-sample block:
     * float32 FIR : ~3200 cycles  (~19 µs)
     * Q15 FIR     : ~1400 cycles  (~8.3 µs) — 2.3x faster
     * Cycle counts depend on data cache hit/miss; run multiple iterations */
    printf("float32: %lu cycles | Q15: %lu cycles\r\n",
           (unsigned long)f32_cycles, (unsigned long)q15_cycles);
}

Exercises

DSP Pipeline Specification Generator

Use this tool to document your CMSIS-DSP signal processing pipeline — signal source, sample rate, data format, filter type and parameters, FFT configuration, and performance targets. Download as Word, Excel, PDF, or PPTX for design documentation or team handoff.

Conclusion & Next Steps

In this article we have worked through the full CMSIS-DSP toolkit from fundamentals to implementation:

• Sampling theory — the Nyquist theorem, aliasing prevention with analogue anti-aliasing filters, and quantisation noise set hard limits that no digital processing can overcome.
• CMSIS-DSP architecture — instance structs keep state external, enabling multiple independent filter instances; compile-time flags (ARM_MATH_CM4) unlock SIMD optimisations.
• FIR filters — arm_fir_init_f32 + arm_fir_f32 implement windowed-sinc designs in block mode; state buffer sizing (NUM_TAPS + BLOCK_SIZE − 1) is critical.
• IIR biquad filters — arm_biquad_cascade_df2T_f32 achieves high-order responses with few coefficients; mind the CMSIS sign convention for feedback coefficients.
• FFT — arm_rfft_fast_f32 + arm_cmplx_mag_f32 + arm_max_f32 form a complete spectral analysis pipeline; windowing is essential to suppress spectral leakage.
• Performance — Q15 on Cortex-M4 with SIMD gives ~2–3x speedup over float32; the DWT cycle counter is the definitive benchmarking tool.