CMSIS Part 13: Low Power & Energy Optimization

WFI, WFE & SLEEPDEEP

WFI (Wait For Interrupt) suspends the CPU until any pending enabled interrupt is detected. WFE (Wait For Event) suspends until an event — which includes interrupts but also hardware events like DMA completion signals and event triggers from other cores in multi-core devices. On single-core Cortex-M, the practical difference is that WFE can be woken by a SEV (Send Event) instruction from any context, including from the same core's ISR, making it useful for spin-wait elimination.

WFI-Based Sleep Loop with SEVONPEND

/**
 * WFI sleep loop: enter sleep after each SysTick, wake on any IRQ.
 * SEVONPEND=1 ensures a pending (but not yet handled) IRQ wakes WFE too.
 *
 * This is the minimal low-power idle — reduces CPU power by ~80% vs
 * a busy-wait loop at the same clock frequency.
 */
#include "core_cm4.h"

void low_power_idle_init(void) {
    /* SEVONPEND: pending interrupt (even before handler entry) wakes WFE */
    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;

    /* SLEEPONEXIT: re-enter sleep automatically on return from ISR.
       Useful when all work is ISR-driven — avoids thread execution overhead */
    /* SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; */  /* Enable if desired */
}

void main_loop_idle(void) {
    /* Drain write buffer before sleeping — prevents late bus errors waking us */
    __DSB();

    /* Enter sleep — CPU halts, clocks continue, all peripherals operational */
    __WFI();

    /* Execution resumes here after any enabled IRQ fires */
}

Entering STOP Mode on STM32 via PWR Registers

STOP mode on STM32 cuts the main voltage regulator to low-power mode and stops all internal clocks except the LSE (32 kHz crystal), LSI, and LPTIM. The SRAM and register contents are preserved. Wakeup sources are RTC alarm, EXTI lines (external pins), LPTIM compare match, or LPUART reception.

/**
 * Enter STM32 STOP2 mode (lowest current with full SRAM retention).
 * Wakeup: RTC alarm (via EXTI20) or EXTI pin.
 *
 * Target: STM32L4 / STM32U5 family.
 * Adjust PWR->CR1 bits for your specific STM32 sub-family.
 */
#include "stm32l4xx.h"   /* or your specific device header */
#include "core_cm4.h"

/* Configure RTC alarm as wakeup source (assumes RTC already initialised) */
static void configure_rtc_wakeup(uint32_t wakeup_seconds) {
    /* Disable RTC write protection */
    RTC->WPR = 0xCAU;
    RTC->WPR = 0x53U;

    /* Set wakeup counter (WUTR) with ~1 Hz clock (RTC_CR WUCKSEL=100) */
    RTC->CR  &= ~RTC_CR_WUTE;                    /* Disable wakeup timer */
    while (!(RTC->ISR & RTC_ISR_WUTWF)) {}        /* Wait for access flag */
    RTC->WUTR = wakeup_seconds - 1U;              /* Counter value        */
    RTC->CR  |= (0x04U << RTC_CR_WUCKSEL_Pos);    /* 1 Hz clock source    */
    RTC->CR  |= RTC_CR_WUTIE | RTC_CR_WUTE;       /* Enable IRQ + timer   */

    /* Re-enable write protection */
    RTC->WPR = 0xFFU;

    /* Route RTC wakeup to EXTI20 so it can wake from STOP */
    EXTI->IMR1  |= EXTI_IMR1_IM20;
    EXTI->RTSR1 |= EXTI_RTSR1_RT20;   /* Rising edge trigger */
}

/**
 * @brief Enter STOP2 mode — returns after wakeup event.
 *        All clocks must be reconfigured after wakeup (PLL relocking).
 */
void enter_stop2_mode(void) {
    /* Select STOP2 mode in PWR CR1 */
    PWR->CR1 = (PWR->CR1 & ~PWR_CR1_LPMS_Msk)
             | (0x02U << PWR_CR1_LPMS_Pos);   /* STOP2 */

    /* Set SLEEPDEEP bit — next WFI enters deep sleep, not sleep */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    /* Drain write buffer, flush pipeline */
    __DSB();
    __ISB();

    /* Enter STOP2 — CPU halts until wakeup event */
    __WFI();

    /* Clear SLEEPDEEP — subsequent WFIs return to normal sleep */
    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;

    /* After STOP2, system clock falls back to MSI (4 MHz default).
       Re-enable PLL and reconfigure clocks for full-speed operation. */
    SystemClock_Config();  /* Vendor-provided or custom clock reconfiguration */
}

/* ---- Application pattern: sample sensors every 5 seconds ---- */
void sensor_application(void) {
    configure_rtc_wakeup(5U);   /* Wake every 5 seconds */

    for (;;) {
        /* Active window: sample sensor, process, transmit BLE */
        float temperature = read_temperature_sensor();
        transmit_ble_advertisement(temperature);

        /* Sleep until next RTC wakeup — ~5 seconds of STOP2 */
        enter_stop2_mode();
    }
}

Peripheral Clock Gating

Even in Run mode, every peripheral clock that is enabled consumes power proportional to its switching activity. On STM32, each peripheral clock is individually gated through the RCC (Reset and Clock Control) peripheral's enable registers. Disabling a peripheral's clock while it is not in use reduces current consumption by eliminating switching activity in the peripheral's clock tree — typically 10–200 µA per peripheral at 3.3V depending on its size and clock frequency.

The pattern is simple: enable the clock before accessing a peripheral, disable it when done. For peripherals used in burst mode (SPI for a sensor read, I2C for an EEPROM write), this can save meaningful average current. The overhead is two register writes and a __DSB() barrier.

APB Clock Gating via RCC Enable Registers

/**
 * Peripheral clock gating: enable/disable APB clocks to save power.
 * Pattern: enable just-in-time, disable after transaction completes.
 *
 * Example: SPI1 (APB2) + I2C1 (APB1) + ADC1 (APB2) clock gating.
 */
#include "stm32f407xx.h"
#include "core_cm4.h"

/* Enable SPI1 clock just before a transaction */
static void spi1_clock_enable(void) {
    RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
    __DSB();   /* Ensure peripheral sees the clock before register access */
}

/* Disable SPI1 clock after transaction is complete */
static void spi1_clock_disable(void) {
    __DSB();               /* Ensure all SPI writes completed first */
    RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
}

/* Disable all unused peripheral clocks at startup */
void clock_gate_unused_peripherals(void) {
    /* APB1: disable peripherals not used in this design */
    RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN    |
                      RCC_APB1ENR_TIM3EN    |
                      RCC_APB1ENR_TIM4EN    |
                      RCC_APB1ENR_USART2EN  |
                      RCC_APB1ENR_USART3EN  |
                      RCC_APB1ENR_UART4EN   |
                      RCC_APB1ENR_DACEN);

    /* APB2: disable unused high-speed peripherals */
    RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN    |
                      RCC_APB2ENR_USART6EN  |
                      RCC_APB2ENR_SPI4EN);

    /* AHB1: disable unused GPIO port clocks */
    RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN  |
                      RCC_AHB1ENR_GPIOCEN  |
                      RCC_AHB1ENR_GPIODEN  |
                      RCC_AHB1ENR_GPIOFEN);
    __DSB();
}

/* Full sensor read burst: enable clocks, read, disable clocks */
float read_temperature_over_spi(void) {
    spi1_clock_enable();

    uint16_t raw = spi_transfer_16bit(0x0000U);

    spi1_clock_disable();

    return (float)raw * 0.0625f;  /* MAX31855 conversion factor */
}

Clock Gating Current Savings by Peripheral

FreeRTOS Tickless Idle

By default, FreeRTOS generates a SysTick interrupt every tick period (typically 1 ms). Even if all tasks are blocked and no work is pending, the SysTick ISR fires 1000 times per second, waking the CPU from sleep, executing the tick increment, and returning to idle. At 10 µA sleep current, these 1000 wakeups per second cost several hundred µA in average active-mode contribution — significant for coin-cell designs.

The FreeRTOS tickless idle feature suppresses SysTick when the idle task runs, programs a low-power timer (LPTIM, RTC) to generate a single wakeup at the next task's deadline, and allows the CPU to remain in sleep for the entire interval. When the low-power timer fires, the RTOS calculates elapsed ticks, updates the kernel time, and resumes the scheduler.

FreeRTOS Tickless Idle with LPTIM Wakeup Timer

/**
 * FreeRTOS tickless idle hook (vPortSuppressTicksAndSleep).
 * Platform: STM32L4 with LPTIM1 as low-power wakeup timer.
 *
 * Enable in FreeRTOSConfig.h:
 *   #define configUSE_TICKLESS_IDLE        1
 *   #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP  2  // minimum ticks
 *
 * FreeRTOS calls this function from the idle task when no higher-priority
 * task is ready and the expected idle time exceeds the minimum threshold.
 */
#include "FreeRTOS.h"
#include "task.h"
#include "stm32l4xx.h"

/* LPTIM1 tick rate: 32768 Hz LSE divided by 32 = 1024 Hz ~ 1 ms/tick */
#define LPTIM_TICK_RATE_HZ  1024U

void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) {
    uint32_t ulLptimCounts;
    TickType_t xModifiableIdleTime;

    /* Calculate LPTIM count for the expected idle period */
    ulLptimCounts = (uint32_t)(xExpectedIdleTime * LPTIM_TICK_RATE_HZ
                                / configTICK_RATE_HZ);

    /* Clamp to LPTIM 16-bit counter maximum */
    if (ulLptimCounts > 0xFFFFU) { ulLptimCounts = 0xFFFFU; }
    if (ulLptimCounts < 2U)      { return; }  /* Too short — skip */

    /* Disable SysTick to prevent it from waking us */
    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;

    /* Configure LPTIM1 compare value for wakeup */
    LPTIM1->CMP = (uint16_t)(ulLptimCounts - 1U);
    LPTIM1->CR |= LPTIM_CR_CNTSTRT;   /* Start LPTIM in continuous mode */

    /* Allow the RTOS to enter sleep — this is where STOP mode is entered */
    xModifiableIdleTime = xExpectedIdleTime;
    configPRE_SLEEP_PROCESSING(xModifiableIdleTime);

    if (xModifiableIdleTime > 0U) {
        __DSB();
        __WFI();   /* Enter sleep until LPTIM compare match or other IRQ */
    }

    configPOST_SLEEP_PROCESSING(xExpectedIdleTime);

    /* Stop LPTIM, read actual elapsed time */
    uint32_t ulCountAfterSleep = LPTIM1->CNT;
    LPTIM1->CR &= ~LPTIM_CR_CNTSTRT;

    /* Calculate actual ticks slept */
    TickType_t xActualSleepTicks = (TickType_t)(ulCountAfterSleep
                                     * configTICK_RATE_HZ / LPTIM_TICK_RATE_HZ);

    /* Re-enable SysTick and advance RTOS tick count */
    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;

    /* Inform FreeRTOS how many ticks elapsed during tickless sleep */
    vTaskStepTick(xActualSleepTicks);
}

Power Domain Management

Modern Cortex-M SoCs (STM32U5, nRF5340, EFR32) partition the chip into multiple independently controllable power domains. A power domain is a group of logic blocks that share a voltage rail and can be powered down as a unit. Peripheral power domain management lets you cut power to an entire subsystem — radio, USB PHY, analog front-end — independent of the CPU core.

Current Measurement & Power Profiling

You cannot optimise what you cannot measure. Power profiling requires a current measurement setup that captures both the high-current active spikes (5–100 mA for 1–10 ms) and the low-current sleep floor (1–100 µA for hundreds of milliseconds). A standard benchtop multimeter averages these together and gives you a meaningless mid-range reading.

The professional approach uses a shunt resistor + oscilloscope (10–100 Ω, captures waveform) or a dedicated power analyser (Otii Arc, Nordic PPK2, Segger J-Trace with energy measurement). For firmware-assisted profiling, toggle a GPIO before and after each power state transition — the oscilloscope shows exactly which firmware activity corresponds to which current peak.

/**
 * Firmware-assisted current measurement anchor points.
 *
 * Connect an oscilloscope probe to PA2 (test pin).
 * Measure current via a shunt resistor in the VDD line.
 * Correlate GPIO state with current trace on a two-channel oscilloscope.
 *
 * GPIO high = active processing / peripheral enabled
 * GPIO low  = sleep / WFI
 */
#include "stm32f407xx.h"
#include "core_cm4.h"

/* Configure PA2 as output for oscilloscope current probe anchor */
static void probe_gpio_init(void) {
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
    __DSB();
    GPIOA->MODER = (GPIOA->MODER & ~GPIO_MODER_MODER2_Msk)
                 | (0x01UL << GPIO_MODER_MODER2_Pos);
    GPIOA->OTYPER &= ~GPIO_OTYPER_OT2;     /* Push-pull */
    GPIOA->BSRR = GPIO_BSRR_BR2;           /* Start low */
}

#define PROBE_HIGH()  (GPIOA->BSRR = GPIO_BSRR_BS2)
#define PROBE_LOW()   (GPIOA->BSRR = GPIO_BSRR_BR2)

void power_profiling_loop(void) {
    probe_gpio_init();

    for (;;) {
        /* Active window: GPIO high = current spike visible on scope */
        PROBE_HIGH();

        /* Do active work: sensor read, computation, transmit */
        float val = read_sensor();
        transmit_result(val);

        /* Mark sleep entry: GPIO falls = sleep current floor on scope */
        PROBE_LOW();
        __DSB();
        __WFI();   /* Sleep until next wakeup — flat line on current trace */

        /* GPIO rises again at next active window start */
    }
}

/**
 * Average current calculation from oscilloscope measurements:
 *
 * I_avg = (I_active * t_active + I_sleep * t_sleep) / (t_active + t_sleep)
 *
 * Example: I_active = 15 mA for 5 ms, I_sleep = 8 µA for 995 ms
 *   I_avg = (15000 µA * 5 + 8 µA * 995) / 1000
 *         = (75000 + 7960) / 1000
 *         = 82.96 µA average
 *
 * Battery life = 1000 mAh / 0.08296 mA = ~12,054 hours = ~502 days
 */

Exercises

Low Power Design Planner

Use this tool to document your project's power management strategy — MCU, power targets, sleep modes, clock gating plan, tickless configuration, and profiling results. Download as Word, Excel, PDF, or PPTX for design-review documentation.

Conclusion & Next Steps

In this article we have assembled the full low-power toolkit for professional ARM Cortex-M firmware:

• The power mode hierarchy — Run, Sleep, Deep Sleep/STOP, Standby, Shutdown — gives you a spectrum of current/latency trade-offs. Choose the deepest mode whose wake latency your application can absorb.
• WFI in the idle loop is the minimum viable optimisation — it costs zero lines of real application code and typically reduces CPU power by 60–80% compared to a busy-wait idle.
• STOP mode with RTC/LPTIM wakeup is the standard pattern for duty-cycled IoT sensors — periods of 1–10 µA sleep interrupted by short active bursts give multi-year coin-cell life.
• Peripheral clock gating is complementary to sleep modes — it saves power in Run mode by eliminating switching activity in inactive peripherals. Disable clocks for every peripheral you are not using at a given moment.
• FreeRTOS tickless idle eliminates unnecessary SysTick wakeups and allows the CPU to remain in sleep for the entire inter-task idle interval — typically 40–70% average current reduction over standard SysTick idle.
• GPIO-anchored current profiling with an oscilloscope gives you accurate active and sleep current figures — the only basis for credible battery-life calculations.
• Average current follows the duty-cycle equation: reducing active time has a proportionally larger impact than reducing active-mode current. Minimise the active window first; then optimise its current.