Part 5: PCB Layout

From Schematic to Copper

Your schematic is done, ERC is clean, and every component has a footprint. Now begins the most creative and consequential phase of hardware design: PCB layout. The decisions you make about layer stack-up, component placement, and routing directly affect your board’s performance, reliability, EMI profile, and manufacturability.

Layer Stack-Ups: 2-Layer vs 4-Layer

The number of copper layers determines your routing flexibility, signal integrity, and cost. For embedded systems, 2-layer and 4-layer are the most common choices.

flowchart TD
    L1["Layer 1 (Top): Signal + Components"] --> L2["Layer 2 (Inner 1): Ground Plane"]
    L2 --> L3["Layer 3 (Inner 2): Power Plane"]
    L3 --> L4["Layer 4 (Bottom): Signal + Components"]
                            

Component Placement

Placement Strategy

Component placement is 70% of a good layout. Place components before routing a single trace. The golden rules:

Decoupling Capacitor Placement

Decoupling capacitors are the most placement-critical components on your board. They provide local charge reservoirs for ICs, filtering high-frequency noise from the power supply. Every VCC pin on every IC needs its own decoupling cap.

import math

# Decoupling capacitor impedance calculator
# Z = 1 / (2π × f × C)
frequencies = [1e6, 10e6, 100e6, 1e9]  # 1 MHz to 1 GHz
cap_values = [100e-9, 10e-9, 100e-12]   # 100nF, 10nF, 100pF

print("Capacitor Impedance at Frequency")
print("=" * 55)
print(f"{'Freq':>10} | {'100nF':>10} | {'10nF':>10} | {'100pF':>10}")
print("-" * 55)

for f in frequencies:
    row = f"{f/1e6:>7.0f}MHz |"
    for c in cap_values:
        z = 1 / (2 * math.pi * f * c)
        row += f" {z:>8.2f}Ω |"
    print(row)

print("\nKey insight: 100nF is excellent at 1-10MHz,")
print("but at 100MHz+ you need smaller caps (100pF)")
print("Use BOTH: 100nF + 100pF in parallel for broadband filtering")

Capacitor Impedance at Frequency
=======================================================
      Freq |      100nF |       10nF |      100pF
-------------------------------------------------------
     1MHz |      1.59Ω |     15.92Ω |   1591.55Ω |
    10MHz |      0.16Ω |      1.59Ω |    159.15Ω |
   100MHz |      0.02Ω |      0.16Ω |     15.92Ω |
  1000MHz |      0.00Ω |      0.02Ω |      1.59Ω |

Key insight: 100nF is excellent at 1-10MHz,
but at 100MHz+ you need smaller caps (100pF)
Use BOTH: 100nF + 100pF in parallel for broadband filtering

Thermal Considerations in Placement

Hot components (voltage regulators, power MOSFETs, motor drivers) need space for heat dissipation. Place them away from temperature-sensitive components (crystals, ADC references) and near board edges where airflow is better.

Routing Techniques

Trace Width & Current Capacity

Trace width determines how much current a trace can safely carry. Too narrow and it overheats; too wide and you waste board space. Use the IPC-2221 formula for calculating trace width.

import math

# IPC-2221 trace width calculator
# For external (outer) layers:
# Area = (I / (k × ΔT^b))^(1/c)  where k=0.048, b=0.44, c=0.725
# Width = Area / (thickness × 1.378)

current = 0.5          # Amps
temp_rise = 10         # °C above ambient (10°C is conservative)
copper_oz = 1          # 1 oz/ft² = 35µm thickness
thickness_mil = 1.378  # 1 oz copper in mils

k, b, c = 0.048, 0.44, 0.725

area = (current / (k * (temp_rise ** b))) ** (1 / c)
width = area / thickness_mil

print(f"Current: {current * 1000:.0f}mA")
print(f"Temp rise: {temp_rise}°C")
print(f"Copper: {copper_oz} oz ({copper_oz * 35}µm)")
print(f"Cross-section area: {area:.2f} mil²")
print(f"Required trace width: {width:.1f} mil ({width * 0.0254:.2f} mm)")

# Common trace widths
print("\n--- Common Trace Width Guidelines ---")
guidelines = [
    ("Signal traces (low current)", "6-8 mil", "0.15-0.2 mm"),
    ("Power traces (< 500mA)", "15-20 mil", "0.4-0.5 mm"),
    ("Power traces (1A)", "30-40 mil", "0.8-1.0 mm"),
    ("Power traces (2A+)", "50-100 mil", "1.3-2.5 mm"),
]
for name, mil, mm in guidelines:
    print(f"  {name}: {mil} ({mm})")

Current: 500mA
Temp rise: 10°C
Copper: 1 oz (35µm)
Cross-section area: 19.04 mil²
Required trace width: 13.8 mil (0.35 mm)

--- Common Trace Width Guidelines ---
  Signal traces (low current): 6-8 mil (0.15-0.2 mm)
  Power traces (< 500mA): 15-20 mil (0.4-0.5 mm)
  Power traces (1A): 30-40 mil (0.8-1.0 mm)
  Power traces (2A+): 50-100 mil (1.3-2.5 mm)

Vias & Layer Transitions

Vias connect traces between layers. Each via adds inductance and breaks the ground plane, so use them intentionally. For high-current paths, use multiple vias in parallel to reduce resistance.

Differential Pairs

Differential pairs carry signals as the voltage difference between two traces (e.g., USB D+/D−, Ethernet TX+/TX−). They must be routed with matched length and controlled impedance.

import math

# Differential pair impedance calculator (microstrip approximation)
# Z_diff ≈ 2 × Z0 × (1 - 0.48 × exp(-0.96 × s/h))
# where Z0 = single-ended impedance, s = trace spacing, h = dielectric height

er = 4.4       # FR4 dielectric constant
h = 0.2        # Dielectric height in mm (4-layer, signal to ground)
w = 0.15       # Trace width in mm
t = 0.035      # Copper thickness in mm (1 oz)
s = 0.15       # Trace spacing in mm (edge to edge)

# Single-ended microstrip impedance (approximate)
z0 = (87 / math.sqrt(er + 1.41)) * math.log(5.98 * h / (0.8 * w + t))
print(f"Single-ended Z0: {z0:.1f}Ω")

# Differential impedance
z_diff = 2 * z0 * (1 - 0.48 * math.exp(-0.96 * s / h))
print(f"Differential Z_diff: {z_diff:.1f}Ω")

# Common targets
print(f"\n--- Target Impedances ---")
print(f"USB 2.0: 90Ω differential")
print(f"USB 3.0: 90Ω differential")
print(f"HDMI: 100Ω differential")
print(f"Ethernet: 100Ω differential")
print(f"LVDS: 100Ω differential")

Single-ended Z0: 71.6Ω
Differential Z_diff: 101.5Ω

--- Target Impedances ---
USB 2.0: 90Ω differential
USB 3.0: 90Ω differential
HDMI: 100Ω differential
Ethernet: 100Ω differential
LVDS: 100Ω differential

Ground Planes & Signal Integrity

A solid, unbroken ground plane is the single most important factor in PCB signal integrity and EMI performance. Every signal trace needs a return current path directly beneath it on the reference plane.

Return Current Paths

flowchart LR
    subgraph Top Layer
        A["IC Pin"] -->|Signal Trace| B["Load"]
    end
    subgraph Ground Plane
        B2["Return Current"] -->|Directly Under Trace| A2["Source GND"]
    end
                            

Crosstalk & Coupling

Crosstalk occurs when a signal on one trace induces noise on an adjacent trace. The coupling strength depends on spacing, parallel run length, and rise time.

import math

# Crosstalk estimation (3W rule)
# Keep trace spacing ≥ 3× trace width for < 5% crosstalk

trace_width = 0.15  # mm
min_spacing_3w = 3 * trace_width  # Edge-to-edge
centre_to_centre = min_spacing_3w + trace_width

print(f"Trace width: {trace_width}mm")
print(f"3W spacing (edge-to-edge): {min_spacing_3w:.2f}mm")
print(f"Centre-to-centre: {centre_to_centre:.2f}mm")

# Crosstalk vs spacing (simplified model)
print(f"\n--- Crosstalk vs Spacing ---")
h = 0.2  # Height above ground plane
for s_factor in [1, 2, 3, 5, 10]:
    s = s_factor * trace_width
    # Simplified: coupling ∝ 1/(1 + (s/h)²)
    coupling = 1 / (1 + (s/h)**2) * 100
    print(f"  Spacing = {s_factor}W ({s:.2f}mm): ~{coupling:.1f}% coupling")

Trace width: 0.15mm
3W spacing (edge-to-edge): 0.45mm
Centre-to-centre: 0.60mm

--- Crosstalk vs Spacing ---
  Spacing = 1W (0.15mm): ~64.0% coupling
  Spacing = 2W (0.30mm): ~30.8% coupling
  Spacing = 3W (0.45mm): ~16.5% coupling
  Spacing = 5W (0.75mm): ~6.6% coupling
  Spacing = 10W (1.50mm): ~1.7% coupling

Thermal Design

Thermal Vias & Exposed Pads

QFN and similar packages have an exposed thermal pad on the bottom that must be soldered to a copper area on the PCB. Thermal vias under this pad transfer heat to inner layers and the back side of the board.

import math

# Thermal via array calculator
# Thermal resistance of a single via:
# R_th = L / (k × A)  where k = copper conductivity

via_drill = 0.3e-3      # 0.3mm drill diameter
via_plating = 25e-6      # 25µm copper plating
board_thickness = 1.6e-3 # 1.6mm standard FR4
k_copper = 385           # W/(m·K) thermal conductivity

# Via copper cross-section (hollow cylinder)
r_outer = via_drill / 2
r_inner = r_outer - via_plating
area_via = math.pi * (r_outer**2 - r_inner**2)

# Thermal resistance per via
r_th_via = board_thickness / (k_copper * area_via)

print(f"Via drill: {via_drill*1e3:.1f}mm")
print(f"Plating: {via_plating*1e6:.0f}µm")
print(f"Copper area: {area_via*1e6:.4f} mm²")
print(f"R_th (single via): {r_th_via:.1f} °C/W")

# Array of vias (parallel thermal resistance)
for n_vias in [1, 3, 5, 9, 16]:
    r_array = r_th_via / n_vias
    print(f"  {n_vias} vias: R_th = {r_array:.1f} °C/W")

print(f"\nRecommendation: 5-9 thermal vias for QFN packages")
print(f"Spacing: 1.0-1.2mm pitch in a grid pattern")

Via drill: 0.3mm
Plating: 25µm
Copper area: 0.0216 mm²
R_th (single via): 192.3 °C/W
  1 vias: R_th = 192.3 °C/W
  3 vias: R_th = 64.1 °C/W
  5 vias: R_th = 38.5 °C/W
  9 vias: R_th = 21.4 °C/W
  16 vias: R_th = 12.0 °C/W

Recommendation: 5-9 thermal vias for QFN packages
Spacing: 1.0-1.2mm pitch in a grid pattern

Copper Pours for Heat Spreading

Large copper areas on outer layers act as heatsinks, spreading heat from hot components across the board surface. Connect thermal pads to copper pours on all layers for maximum heat dissipation.

Design Rule Checks

Before generating manufacturing files, run a comprehensive Design Rule Check (DRC). This catches clearance violations, unrouted nets, minimum trace widths, and via drill size errors.

Exercises

PCB Stackup Planner Tool

Use this tool to document your PCB layer stack-up and design rules for manufacturing hand-off.

Conclusion & Next Steps

You now command the full PCB layout workflow — from choosing the right layer stack-up through strategic component placement, trace routing with impedance control, ground plane integrity, thermal management, and final DRC verification. Your layouts are ready for manufacturing.