ARM Assembly Part 17: Inline Assembly, GCC/Clang & C Interop

Introduction & When to Use Inline Asm

Use inline assembly when: you need a single hardware instruction the compiler won't emit (e.g., clz, rbit, dmb); you need precise register placement without function call overhead; or you need compiler-visible effects on memory ordering. Avoid inline asm for anything longer than ~10 instructions — a separate .S file is cleaner, testable, and debuggable.

Basic asm() Syntax

// Basic asm — no operands, just instruction string
// Primarily for assembly directives or ultra-simple one-liners
// GCC may reorder or eliminate basic asm blocks — rarely what you want

void disable_irq(void) {
    asm("msr daifset, #2");    // Disable IRQ (sets DAIF.I)
}

void enable_irq(void) {
    asm("msr daifclr, #2");    // Enable IRQ (clears DAIF.I)
}

// Basic asm with multiple instructions (semicolon or \n separated)
void wfi_sleep(void) {
    asm("dsb sy\n\t"          // Data sync barrier
        "wfi");               // Wait for interrupt
}

Extended asm() — Operands & Constraints

Extended asm has the form: asm [volatile] ("template" : [outputs] : [inputs] : [clobbers]). The template uses %0, %1, … as placeholders for operands listed in order: outputs first, then inputs. On AArch64 use %w0 for 32-bit (W-register) access and %x0 for explicit 64-bit.

Output Constraints

#include <stdint.h>

// "=r" — any general-purpose register, write-only output
static inline uint64_t read_cntvct(void) {
    uint64_t val;
    asm volatile("mrs %0, cntvct_el0" : "=r"(val));
    return val;
}

// "+r" — read-write register (input AND output to same register)
static inline uint32_t bit_reverse(uint32_t x) {
    asm volatile("rbit %w0, %w0" : "+r"(x));
    return x;
}

// "=&r" — early-clobber: output register must not overlap any input
// Required when output may be written before all inputs are consumed
static inline void str_exclusive(uint32_t val, volatile uint32_t *addr,
                                  int *status) {
    asm volatile("stxr  %w0, %w2, [%1]"
                 : "=&r"(*status)          // =& prevents overlap with %1/%2
                 : "r"(addr), "r"(val)
                 : "memory");
}

Input Constraints

// "r" — any GP register (input)
// "i" — immediate integer (compile-time constant only)
// "m" — memory operand (produces address for asm use)
// "n" — numeric constant (immediate, no register allocated)

static inline int count_leading_zeros(uint64_t x) {
    int result;
    asm("clz %0, %1" : "=r"(result) : "r"(x));
    return result;
}

// Using "i" constraint for immediate (shift amount must be constant)
static inline uint32_t rotate_right(uint32_t x, int shift) {
    // Compiler substitutes literal integer into template at compile time
    uint32_t out;
    asm("ror %w0, %w1, #%2"
        : "=r"(out)
        : "r"(x), "i"(shift));
    return out;
}

// Tied input (digit = output index): reuse same register
static inline uint32_t set_bit(uint32_t val, uint32_t bit) {
    asm("orr %w0, %w0, %w1"
        : "+r"(val)            // %0: read-write (tied input)
        : "r"(1u << bit));
    return val;
}

Clobbers & Memory

// Clobbers tell the compiler which registers/flags the asm modifies
// WITHOUT expressing them as outputs — so compiler saves/restores them

// "cc" clobber: asm modifies condition flags
static inline int signed_saturate(int x, int limit) {
    int result;
    asm volatile(
        "cmp  %1, %2\n\t"
        "csel %0, %1, %2, lt"    // Select min(x, limit)
        : "=r"(result)
        : "r"(x), "r"(limit)
        : "cc");                  // CMP modifies NZCV flags
    return result;
}

// "memory" clobber: asm reads/writes memory not named in operands
// Forces compiler to flush/reload all live values around the asm
#define mb()  asm volatile("dmb ish"   : : : "memory")
#define wmb() asm volatile("dmb ishst" : : : "memory")
#define rmb() asm volatile("dmb ishld" : : : "memory")
#define isb() asm volatile("isb"       : : : "memory")

// Combine register + memory clobbers: context switch saves x19-x28 etc.
void switch_context(uint64_t *save_sp, uint64_t *load_sp) {
    asm volatile(
        "stp  x19, x20, [%0, #0]\n\t"
        "stp  x21, x22, [%0, #16]\n\t"
        "stp  x23, x24, [%0, #32]\n\t"
        "mov  %0, sp\n\t"               // Save current SP
        "mov  sp, %1\n\t"               // Load new SP
        "ldp  x19, x20, [sp, #0]\n\t"
        "ldp  x21, x22, [sp, #16]\n\t"
        "ldp  x23, x24, [sp, #32]"
        :
        : "r"(save_sp), "r"(*load_sp)
        : "x19","x20","x21","x22","x23","x24","memory","cc"
    );
}

Memory Barriers via Inline Asm

// Linux kernel barrier pattern (arch/arm64/include/asm/barrier.h style)
#define smp_mb()     asm volatile("dmb ish"   : : : "memory")
#define smp_wmb()    asm volatile("dmb ishst" : : : "memory")
#define smp_rmb()    asm volatile("dmb ishld" : : : "memory")
#define dma_wmb()    asm volatile("dmb oshst" : : : "memory")  // outer shareable

// READ_ONCE and WRITE_ONCE equivalents (prevent compiler reordering)
#define READ_ONCE(x) \
    ({ typeof(x) __val; asm volatile("" : "=r"(__val) : "0"(x)); __val; })
#define WRITE_ONCE(x, val) \
    asm volatile("" : : "r"((typeof(x))(val)) : "memory")

// Acquire/release atomics using LDAR/STLR
static inline uint64_t load_acquire(const volatile uint64_t *addr) {
    uint64_t val;
    asm volatile("ldar %0, [%1]" : "=r"(val) : "r"(addr) : "memory");
    return val;
}

static inline void store_release(volatile uint64_t *addr, uint64_t val) {
    asm volatile("stlr %1, [%0]" : : "r"(addr), "r"(val) : "memory");
}

Atomic Operations (LDXR/STXR)

// CAS (Compare And Swap) using exclusive monitor
// AArch64 also has ARMv8.1 LSE atomics: CAS, SWP, LDADD (preferred where available)
static inline int atomic_cmpxchg32(volatile int *ptr, int old_val, int new_val) {
    int result;
    int tmp;
    asm volatile(
    "1: ldxr  %w0, [%2]\n\t"       // Load exclusive: result = *ptr
        "cmp   %w0, %w3\n\t"       // result == old_val?
        "b.ne  2f\n\t"             // No: bail out
        "stxr  %w1, %w4, [%2]\n\t" // Yes: try store exclusive
        "cbnz  %w1, 1b\n\t"        // Retry if store exclusive failed
    "2: clrex"                     // Clear exclusive if bailed out
        : "=&r"(result), "=&r"(tmp)
        : "r"(ptr), "r"(old_val), "r"(new_val)
        : "cc", "memory"
    );
    return result;                  // Returns old value (Linux cmpxchg convention)
}

// ARMv8.1 LSE: preferred on Cortex-A55+, Neoverse, Apple Silicon
// Requires -march=armv8.1-a+lse or target_feature attribute
#ifdef __ARM_FEATURE_ATOMICS
static inline int atomic_cmpxchg32_lse(volatile int *ptr, int old_val, int new_val) {
    asm volatile("cas %w0, %w2, [%1]"
                 : "+r"(old_val)
                 : "r"(ptr), "r"(new_val)
                 : "memory");
    return old_val;
}
#endif

NEON & Compiler Intrinsics from C

// Header: <arm_neon.h> — included automatically with -mfpu=neon or -march=armv8-a
#include <arm_neon.h>
#include <stdint.h>

// Horizontal sum of 4 floats using intrinsics (no inline asm needed)
float sum4(const float *arr) {
    float32x4_t v = vld1q_f32(arr);       // Load 4 floats into NEON register
    float32x2_t lo = vget_low_f32(v);
    float32x2_t hi = vget_high_f32(v);
    float32x2_t sum = vpadd_f32(lo, hi);   // Pairwise add
    sum = vpadd_f32(sum, sum);             // Final pair add
    return vget_lane_f32(sum, 0);
}

// Dot product using FMLA (fused multiply-accumulate)
float dot_product(const float *a, const float *b, int n) {
    float32x4_t acc = vdupq_n_f32(0.0f);
    for (int i = 0; i < n - 3; i += 4) {
        float32x4_t va = vld1q_f32(a + i);
        float32x4_t vb = vld1q_f32(b + i);
        acc = vfmaq_f32(acc, va, vb);      // acc += va * vb (FMLA)
    }
    return vaddvq_f32(acc);                // Horizontal sum (ARMv8.1 addv)
}

// Mixing intrinsics and inline asm for timing (CNTVCT_EL0 not in arm_neon.h)
#include <time.h>
static inline uint64_t read_timer(void) {
    uint64_t t;
    asm volatile("mrs %0, cntvct_el0" : "=r"(t));
    return t;
}

Common Pitfalls & Debugging

Case Study: Linux Kernel's Inline Assembly

Hands-On Exercises

Conclusion & Next Steps

We covered inline assembly for ARM: basic vs extended asm syntax, output/input/clobber constraints with =r, +r, =&r, r, i, m and cc/memory, atomic LDXR/STXR loops and LSE CAS, memory barrier macros, LDAR/STLR acquire-release patterns, and NEON intrinsics as a higher-level alternative. Through the Linux kernel case study, we saw how production code uses every constraint pattern for correctness on SMP systems — and through the exercises, you practiced writing constraint-correct wrappers, implementing a ticket spinlock, and benchmarking inline asm against compiler autovectorization.